- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376425 > UPD30550F2-400-NN1 (NEC Corp.) VR5500⑩ 64-/32-BIT MICROPROCESSOR PDF資料下載
參數(shù)資料
| 型號： | UPD30550F2-400-NN1 |
| 廠商： | NEC Corp. |
| 英文描述： | VR5500⑩ 64-/32-BIT MICROPROCESSOR |
| 中文描述： | VR5500⑩64-/32-BIT微處理器 |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 569K |
| 代理商： | UPD30550F2-400-NN1 |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
DATA SHEET
PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
μ
PD30550
V
R
5500
TM
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The
μ
PD30550 (V
R
5500) is a member of the V
R
Series
TM
of RISC (Reduced Instruction Set Computer)
microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by
MIPS
TM
.
The V
R
5500 allows selection of a 64-bit or 32-bit bus width for the system interface, and can operate using
protocols compatible with the V
R
5000 Series
TM
and V
R
5432
TM
.
Detailed function descriptions are provided in the
V
R
5500 User’s Manual (U16044E)
user’s manual. Be sure to read the manual before designing.
FEATURES
64-/32-bit address/data multiplexed bus
MIPS 64-bit RISC architecture
High-speed operation processing
Two-way superscaler super pipeline
300 MHz product:
603 MIPS
400 MHz product:
804 MIPS
High-speed translation lookaside buffer (TLB)
(48 entries)
Address space
Physical:
36 bits (64-bit bus selected)
32 bits (32-bit bus selected)
Virtual:
40 bits (in 64-bit mode)
31 bits (in 32-bit mode)
On-chip floating-point unit (FPU)
Supports sum-of-products instructions
On-chip primary cache memory
(instruction/data: 32 KB each)
2-way set associative
Supports line lock feature
Bus width selectable during reset
Bus protocol compatibility with existing products
retained
Maximum operating frequency
300 MHz product: Internal 300 MHz, external 133
MHz
400 MHz product: Internal 400 MHz, external 133
MHz
External/internal multiplication factor selectable from
×
2 to
×
5.5 by increments of .5
Conforms to MIPS I, II, III, IV and MIPS64 instruction
sets. Instruction set extensions supported include
product-sum operation instruction, rotate instruction,
register scan instruction, and instruction for low power
mode.
Hardware debug functions supported are N-Wire and
JTAG.
Supply voltage
Core block:
1.5 V
±
5% (300 MHz product)
1.6 to 1.7 V (400 MHz product)
I/O block:
3.3 V
±
5%, 2.5 V
±
5%
Document No. U15700EJ1V0DS01 (2nd edition)
Date Published September 2002 N CP(K)
Printed in USA
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
2002
2001
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD4168 | 8,192 x 8-BIT NMOS XRAM |
| UPD4168C-15 | 8,192 x 8-BIT NMOS XRAM |
| UPD4168C-20 | 8,192 x 8-BIT NMOS XRAM |
| UPD4168C | 8,192 x 8-BIT NMOS XRAM |
| UPD4168C-12 | 8,192 x 8-BIT NMOS XRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD30700LRS-225 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| UPD30700LRS-250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| UPD30700RS-180 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| UPD30700RS-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| UPD30710A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VR Series Pamphlet | Pamphlet[12/2002] |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。