25
LIST OF TABLES (2/4)
Table. No.
Title
Page
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
Shift Instruction (Extended ISA)..............................................................................................................
Multiply/Divide Instructions.....................................................................................................................
Multiply/Divide Instructions (Extended ISA)............................................................................................
Number of Stall Cycles in Multiply and Divide Instructions.....................................................................
Number of Delay Slot Cycles in Jump and Branch Instructions .............................................................
Jump Instructions ...................................................................................................................................
Branch Instructions.................................................................................................................................
Branch Instructions (Extended ISA)........................................................................................................
Special Instructions ................................................................................................................................
Special Instructions (Extended ISA).......................................................................................................
System Control Coprocessor (CP0) Instructions....................................................................................
89
90
90
91
92
93
94
95
96
96
97
4-1
4-2
4-3
4-4
Description of Pipeline Activities during Each Stage..............................................................................
Correspondence of Pipeline Stage to Interlock and Exception Condition ..............................................
Description of Pipeline Exception...........................................................................................................
Pipeline Interlock ....................................................................................................................................
101
110
111
111
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
Comparison of useg and xuseg..............................................................................................................
32-bit and 64-bit Supervisor Mode Segments ........................................................................................
32-bit Kernel Mode Segments................................................................................................................
64-bit Kernel Mode Segments................................................................................................................
Cacheability and the xkphys Address Space .........................................................................................
V
R
4102 Physical Address Space............................................................................................................
ROM Addresses (when using 16-bit data bus).......................................................................................
ROM Addresses (when using 32-bit data bus).......................................................................................
Internal I/O Space 1................................................................................................................................
Internal I/O Space 2................................................................................................................................
DRAM Addresses (when using 16-bit data bus).....................................................................................
DRAM Addresses (when using 32-bit data bus).....................................................................................
Cache Algorithm.....................................................................................................................................
Mask Values and Page Sizes.................................................................................................................
122
126
130
132
133
136
137
137
139
139
140
140
145
147
6-1
6-2
6-3
6-4
6-5
CP0 Exception Processing Registers.....................................................................................................
Cause Register Exception Code Field....................................................................................................
64-Bit Mode Exception Vector Base Addresses.....................................................................................
32-Bit Mode Exception Vector Base Addresses.....................................................................................
Exception Priority Order..........................................................................................................................
159
166
174
174
176
10-1
10-2
10-3
10-4
10-5
10-6
BCU Registers........................................................................................................................................
Address Bit Correspondence between ADD Bus and External Devices ................................................
Address Connection Table with External Devices..................................................................................
Access Size Restrictions for Address Spaces........................................................................................
Summary of ROM Modes .......................................................................................................................
Example of Bit Inversion in Data in V
R
4102 and at DATA [15:0] Pins....................................................
235
246
246
247
248
250