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參數(shù)資料
| 型號(hào)： | UPD44321361GF-A75 |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION |
| 中文描述： | 32兆位ZEROSB SRAM的流動(dòng)經(jīng)手術(shù) |
| 文件頁(yè)數(shù)： | 15/24頁(yè) |
| 文件大?。?/td> | 299K |
| 代理商： | UPD44321361GF-A75 |
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15
Data Sheet M15958EJ5V0DS
μ
PD44321181, 44321361
Read and Write Cycle
Parameter
Symbol
-A75 (117 MHz)
Unit
Notes
Standard
Alias
MIN.
MAX.
Cycle time
TKHKH
TCYC
8.6
–
ns
Clock access time
TKHQV
TCD
–
7.5
ns
Output enable access time
TGLQV
TOE
–
3.5
ns
Clock high to output active
TKHQX1
TDC1
2.5
–
ns
1, 2
Clock high to output change
TKHQX2
TDC2
2.5
–
ns
Output enable to output active
TGLQX
TOLZ
0
–
ns
1
Output disable to output High-Z
TGHQZ
TOHZ
0
3.5
ns
1
Clock high to output High-Z
TKHQZ
TCZ
2.5
5
ns
1, 2
Clock high pulse width
TKHKL
TCH
2.5
–
ns
Clock low pulse width
TKLKH
TCL
2.5
–
ns
Setup times
Address
TAVKH
TAS
1.5
–
ns
Address advance
TADVVKH
TADVS
Clock enable
TEVKH
TCES
Chip enable
TCVKH
TCSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
Hold times
Address
TKHAX
TAH
0.5
–
ns
3
Address advance
TKHADVX
TADVH
(1.0)
(–)
Clock enable
TKHEX
TCEH
Chip enable
TKHCX
TCSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Power down entry time
TZZE
TZZE
–
8.6
ns
Power down recovery time
TZZR
TZZR
–
8.6
ns
Notes 1.
Transition is measured
±
200 mV from steady state.
2.
To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than
TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus
contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (T
A
min.,
V
DD
max.) than TKHQZ, which is a max. parameter (worse case at T
A
max., V
DD
min.).
3.
These values apply when V
DD
= 3.3 V
±
0.165 V with a 3.3 V LVTTL interface, or when V
DD
= 2.5 V
±
0.125 V with a 2.5 V LVTTL interface.
Values in parentheses apply when V
DD
= 3.3 V
±
0.165 V with a 2.5 V LVTTL interface.
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