參數(shù)資料
型號(hào)： UPD4482321GF-C75
廠商： NEC Corp.
英文描述： 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
中文描述： 800萬(wàn)位CMOS同步快速靜態(tài)存儲(chǔ)器流經(jīng)手術(shù)
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 370K
代理商： UPD4482321GF-C75
15
μ
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Read and Write Cycle (2.5 V LVTTL Interface)
Parameter
Symbol
-A65, -A75, -C75
-A85, -C85
Unit Note
-A65Y, -A75Y, -C75Y
-A85Y, -C85Y
(117 MHz)
(100MHz)
Standard
Alias
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TCYC
8.6
–
10.0
–
ns
Clock access time
TKHQV
TCD
–
7.5
–
8.5
ns
Output enable access time
TGLQV
TOE
–
3.5
–
3.5
ns
Clock high to output active
TKHQX1
TDC1
2.5
–
2.5
–
ns
Clock high to output change
TKHQX2
TDC2
2.5
–
2.5
–
ns
Output enable to output active
TGLQX
TOLZ
0
–
0
–
ns
Output disable to output High-Z TGHQZ
TOHZ
0
3.5
0
3.5
ns
Clock high to output High-Z
TKHQZ
TCZ
2.5
5.0
2.5
5.0
ns
Clock high pulse width
TKHKL
TCH
2.5
–
2.5
–
ns
Clock low pulse width
TKLKH
TCL
2.5
–
2.5
–
ns
Setup times Address
TAVKH
TAS
1.5
–
2.0
–
ns
Address status
TADSVKH
TSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
Address advance TADVVKH
–
Chip enable
TEVKH
–
Hold times
Address
TKHAX
TAH
0.5
–
0.5
–
ns
Address status
TKHADSX
TSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Address advance TKHADVX
–
Chip enable
TKHEX
–
Power down entry time
TZZE
TZZE
–
8.6
–
10.0
ns
Power down recovery time
TZZR
TZZR
–
8.6
–
10.0
ns
相關(guān)PDF資料
PDF描述
UPD4482321GF-C85 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
UPD4482161 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
UPD4482161GF-C75 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
UPD4482161GF-C85 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
UPD4482321 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
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