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參數(shù)資料
| 型號(hào)： | UPD4482321GF-C75 |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION |
| 中文描述： | 800萬(wàn)位CMOS同步快速靜態(tài)存儲(chǔ)器流經(jīng)手術(shù) |
| 文件頁(yè)數(shù)： | 9/28頁(yè) |
| 文件大?。?/td> | 370K |
| 代理商： | UPD4482321GF-C75 |
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9
μ
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
[
μ
PD4482321,
μ
PD4482361]
Address
register
Binary
counter
and logic
CLR
Q0
Q1
Byte 1
Write register
Byte 1
Write driver
8/9
Byte 2
Write register
Byte 2
Write driver
8/9
Byte 3
Write register
Byte 3
Write driver
8/9
Byte 4
Write register
Byte 4
Write driver
32/36
8/9
Enable
register
Row and column
decoders
Input
register
Output
buffer
32/36
18
18
16
18
A0, A1
A1
’
A0
’
4
32/36
A0 to A17
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BW3
/BW4
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O32
I/OP1 to I/OP4
ZZ
Power down control
Memory cell array
1,024 rows
256
×
32 columns
(8,388,608 bits)
256
×
36 columns
(9,437,184 bits)
Burst Sequence
[
μ
PD4482321,
μ
PD4482361]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A17 to A2, A1, A0
1st Burst Address
A17 to A2, A1, /A0
2nd Burst Address
A17 to A2, /A1, A0
3rd Burst Address
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE =
V
SS
)
External Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
1st Burst Address
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
2nd Burst Address
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
3rd Burst Address
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD4482321GF-C85 | 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION |
| UPD4482161 | 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION |
| UPD4482161GF-C75 | 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION |
| UPD4482161GF-C85 | 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION |
| UPD4482321 | 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION |
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