參數(shù)資料
型號: UPD4482363GF-A50Y
廠商: NEC Corp.
英文描述: 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT
中文描述: 800萬位CMOS同步快速靜態(tài)存儲(chǔ)器流水線操作雙循環(huán)取消選擇
文件頁數(shù): 18/28頁
文件大小: 300K
代理商: UPD4482363GF-A50Y
1
D
μ
P
TKHKH
TKLKH
TKHKL
TAVKH
TEVKH
TKHEX
TGHQZ
Q1(A1)
Q1(A2)
Q1(A3)
Q1(A4)
A3
A2
TDVKH TKHDX
TKHAX
TADSVKH TKHADSX
CLK
/AC
Address
/CEs
Note2
/G
Data In
/BWE
Note1
/BWs
/GW
Note1
Data Out
TWVKH
Notes
2.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
3.
Outputs are disabled within two clock cycles after deselect.
4.
If /GW is set to low level or /BWE is set to low level and one of /BW1 to /BW4 is set to low level,
Q1(A9) is not output.
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
SINGLE READ / WRITE CYCLE
A4
A5
A6
A7
A1
A8
A9
TWVKH
TKHWX
Q1(A7)
Q1(A8)
Q1(A9)
D1(A5)
D1(A6)
D1(A7)
TGLQX
TKHQV
TGLQV
TKHQZ
Remark
/AP is HIGH and /ADV is don't care.
TKHWX
Note3
High-Z
High-Z
High-Z
High-Z
Note4
Note4
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