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參數(shù)資料
| 型號(hào)： | UPD4482363GF-A50Y |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT |
| 中文描述： | 800萬(wàn)位CMOS同步快速靜態(tài)存儲(chǔ)器流水線操作雙循環(huán)取消選擇 |
| 文件頁(yè)數(shù)： | 7/28頁(yè) |
| 文件大?。?/td> | 300K |
| 代理商： | UPD4482363GF-A50Y |
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7
Data Sheet M14904EJ3V0DS
μ
PD4482163, 4482183, 4482323, 4482363
Block Diagrams
[
μ
PD4482163,
μ
PD4482183]
Address
Registers
Binary
Counter
and Logic
CLR
Q0
Q1
Byte 1
Write Register
Byte 1
Write Driver
8/9
Byte 2
Write Register
Byte 2
Write Driver
8/9
Enable
Register
Row and Column
Decoders
Memory cell array
1,024 rows
512
×
16 columns
(8,388,608 bits)
512
×
18 columns
(9,437,184 bits)
Output
Registers
Output
Buffers
Input
Registers
16/18
17
19
A0, A1
A1’
A0’
16/18
2
16/18
A0 to A18
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O16
I/OP1 to I/OP2
ZZ
Power Down Control
19
Burst Sequence
[
μ
PD4482163,
μ
PD4482183]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A18 to A2, A1, A0
1st Burst Address
A18 to A2, A1, /A0
2nd Burst Address
A18 to A2, /A1, A0
3rd Burst Address
A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
1st Burst Address
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
2nd Burst Address
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
3rd Burst Address
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
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| UPD4482183GF-A60 | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT |
| UPD4482363GF-A60 | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT |
| UPD4482183GF-A60Y | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT |
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| UPD45128163G5 | 制造商:Renesas Electronics Corporation 功能描述:128 MBIT SDRAM |
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| UPD4516161AG5A109NF | 制造商:NEC Electronics Corporation 功能描述: |
| UPD4516161AG5-A10-9NF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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