- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384043 > UPD4564163 (Elpida Memory, Inc.) 64M-bit Synchronous DRAM 4-bank, LVTTL PDF資料下載
參數(shù)資料
| 型號： | UPD4564163 |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 6400位同步DRAM 4銀行，LVTTL |
| 文件頁數(shù)： | 21/85頁 |
| 文件大?。?/td> | 919K |
| 代理商： | UPD4564163 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
Data Sheet E0149N10
21
μ
PD4564441, 4564841, 4564163
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A13 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
: A13 through A7
/CAS latency : A6 through A4
Wrap type
: A3
Burst length : A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device.
13.3 Relationship
between Frequency and Latency
shows the relationship of /CAS latency to the clock period and the speed grade of
the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved
addressing.
7.1 Burst Length and Sequence
shows the addressing sequence for each burst length using them.
Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD4564163G5 | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD4564441 | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD4564841 | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD485505 | LINE BUFFER 5K-WORD BY 8-BIT |
| UPD485505G-25 | LINE BUFFER 5K-WORD BY 8-BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD4564163G5-A10B-9JF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 4M x 16, 54 Pin, Plastic, TSOP |
| UPD4564323G5-A10BL-9HJ | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD45D128442G5C759LG | 制造商:NEC 功能描述:* |
| UPD4701AC-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4702C-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。