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參數(shù)資料
| 型號(hào)： | UPD4564323G5-A10-9JH |
| 廠商： | NEC Corp. |
| 英文描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 6400位同步DRAM 4銀行，LVTTL |
| 文件頁(yè)數(shù)： | 18/84頁(yè) |
| 文件大?。?/td> | 1048K |
| 代理商： | UPD4564323G5-A10-9JH |
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Data Sheet M14376EJ2V0DS00
18
μ
PD4564323 for Rev.
E
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1)
To stabilize internal circuits, when power is applied, a 100
μ
s or longer pause must precede any signal toggling.
(2)
After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3)
Once the precharge is completed and the minimum t
RP
is satisfied, the mode register can be programmed. After
the mode register set cycle, t
RSC
(2 CLK minimum) pause must be satisfied as well.
(4)
Two or more CBR (Auto) refresh must be performed.
Remarks 1.
The sequence of Mode register programming and Refresh above may be transposed.
2.
CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
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