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參數(shù)資料
| 型號： | UPD4564323G5-A10-9JH |
| 廠商： | NEC Corp. |
| 英文描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 6400位同步DRAM 4銀行，LVTTL |
| 文件頁數(shù)： | 9/84頁 |
| 文件大?。?/td> | 1048K |
| 代理商： | UPD4564323G5-A10-9JH |
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Data Sheet M14376EJ2V0DS00
9
μ
PD4564323 for Rev.
E
2. Commands
Mode register set command
(/CS, /RAS, /CAS, /WE = Low)
The
μ
PD4564323 has a mode register that defines how the device
operates. In this command, A0 through A10, BA0 and BA1 are the data input
pins. After power on, the mode register set command must be executed to
initialize the device.
The mode register can be set only when all banks are in idle state.
During 2 CLK (t
RSC
) following this command, the
μ
PD4564323 cannot
accept any other commands.
Fig.1
Mode register set command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Activate command
(/CS, /RAS = Low, /CAS, /WE = High)
The
μ
PD4564323 has four banks, each with 4,096 rows.
This command activates the bank selected by BA0 and BA1 and a row
address selected by A0 through A10.
This command corresponds to a conventional DRAM’s /RAS falling.
Fig.2 Row address strobe and
bank activate command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
(Bank select)
Row
Row
Precharge command
(/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0 and
BA1. When A10 is High, all banks are precharged, regardless of BA0 and
BA1. When A10 is Low, only the bank selected by BA0 and BA1 is
precharged.
After this command, the
μ
PD4564323 can’t accept the activate command to
the precharging bank during t
RP
(precharge to activate command period).
This command corresponds to a conventional DRAM’s /RAS rising.
Fig.3
Precharge command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
(Precharge select)
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