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參數(shù)資料
| 型號： | UPD4564841G5 |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 6400位同步DRAM 4銀行，LVTTL |
| 文件頁數(shù)： | 26/85頁 |
| 文件大?。?/td> | 919K |
| 代理商： | UPD4564841G5 |
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Data Sheet E0149N10
26
μ
PD4564441, 4564841, 4564163
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or
Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is
selected and begins automatically.
The t
RAS
must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after t
RP
has been
satisfied.
In write cycle, the t
DAL
must be satisfied to issue the next activate command to the bank being precharged.
The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode
register and whether read or write cycle.
10.1 Read with Auto Precharge
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS
latency of 3) the last data word output.
QB1
QB2
QB3
QB4
Auto precharge starts
READA B
Hi-Z
QB1
QB2
QB3
QB4
Auto precharge starts
READA B
Hi-Z
DQ
Command
DQ
Command
/CAS latency = 2
/CAS latency = 3
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4
(t
RAS
must be satisfied)
T9
Remark
READA means Read with Auto precharge
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