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參數(shù)資料
| 型號： | UPD46128512-X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存800萬字由16位溫度范圍 |
| 文件頁數(shù)： | 15/82頁 |
| 文件大?。?/td> | 817K |
| 代理商： | UPD46128512-X |
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Preliminary Data Sheet M17507EJ2V0DS
15
μ
PD46128512-X
4. Burst Operation
Burst operation is valid when burst mode is set through mode register.
4.1 Features of Burst Operation
Function
Features
Burst Length
8, 16, Continuous
Read Latency
5, 6, 7, 8, 9, 10
Write Latency
4, 5, 6, 7, 8, 9
Burst Sequence
Linear
Single Write
Single Write, Burst Write
Valid Clock Edge
Rising Edge, Falling Edge
4.2 Burst Length
Burst length is the number of word to be read or written during synchronous burst read/write operation as the result of a
single address latch cycle. It can be set on 8, 16words boundary or continuous for entire address through Mode Register
Set sequence. Starting from initial address being latched, device internal address counter assign +1 to the previous
address until reaching the end of boundary address. After completing read data out or write data latch for the set burst
length, operation automatically end except for continuous burst. When continuous burst length is set, read /write is
endless unless it is terminated by the rising edge of /CE1.
4.3 Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through Mode Register Set sequence after power application.
Once RL is set through Mode Register Set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL
1.
Latency Count
Grade
Clock
Asynchronous
Read Latency
Write Latency
Note
Frequency
access time
-E9X
<108 MHz
70 ns
8, 9, 10
7, 8, 9
-E10X
85 ns
10
9
-E9X, -E11X
<83 MHz
70 ns
7, 8, 9, 10
6, 7, 8, 9
-E10X, -E12X
85 ns
8, 9, 10
7, 8, 9
-E9X, -E11X
<66 MHz
70 ns
6, 7, 8, 9, 10
5, 6, 7, 8, 9
-E10X, -E12X
85 ns
7, 8, 9, 10
6, 7, 8, 9
-E9X, -E11X
<52 MHz
70 ns
5, 6, 7, 8, 9, 10
4, 5, 6, 7, 8, 9
-E10X, -E12X
85 ns
5, 6, 7, 8, 9, 10
4, 5, 6, 7, 8, 9
Note
Write Latency = Read Latency
1
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