- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379499 > UPD46128953-E15X (NEC Corp.) 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION PDF資料下載
參數(shù)資料
| 型號： | UPD46128953-E15X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍 |
| 文件頁數(shù)： | 25/60頁 |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-E15X |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
Preliminary Data Sheet M17506EJ1V1DS
25
μ
PD46128953-X
Table 4-4. Mode Register Code3 Definition (6th Bus Cycle)
Data Code
Symbol
Function
Value
Description
A/DQ2 to A/DQ0
RL
Read Latency
000
Reserved
001
Reserved
010
Reserved
011
Reserved
100
6
101
7
110
8
111
Reserved
A/DQ3
N/A
N/A
1
Reserved
A/DQ4
SW
Single Write
0
Burst Read & Burst Write
1
Reserved
A/DQ5
VE
Valid Clock Edge
0
Reserved
1
Rising Edge
A/DQ6
RP
Reset to Asynchronous
1
Reserved
A/DQ7
WC
/WE Control
0
/WE Pulse Control
1
Reserved
A/DQ21 to A/DQ8
1
Reserved
DQ31 to DQ22
1
Reserved
4. 1. 2
Mode Register Setting/Reading
Select whether to set the mode register or read the set contents of the register by this item.
If 1 is input to A/DQ0 in the 4th cycle, the mode register setting mode is set. If 0 is input to A/DQ0 in the 4th cycle, the
mode register reading mode is set.
For how to read the mode register, refer to
4.2 Mode Register Reading
.
4. 1. 3
Partial refresh Density
The partial refresh area is set by this item. If 00 are input to A/DQ1 and A/DQ0 in the 5th cycle, it is set that 32M bits
are retained. If 01 are input to A/DQ1 and A/DQ0 in the 5th cycle, it is set that 16M bits are retained. If 10 are input to
A/DQ1 and A/DQ0 in the 5th cycle, it is set that 64M bits are retained. If 11 are input to A/DQ1 and A/DQ0 in the 5th
cycle, it is set that all bits are not retained.
4. 1. 4
Burst length
The burst length is set by this item. If 010 are input to A/DQ4, A/DQ3, and A/DQ2 in the 5th cycle, the burst length is
set to 8. This product supports only a burst length of 8.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD46128953-X | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| UPD4616112F9-B95LX-BC2 | 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| UPD4616112F9-B85LX-BC2 | 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| UPD4616112F9-BC80-BC2 | 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT |
| UPD4616112 | 16M-BIT CMOS MOBILE SPECIFIED RAM 1M-WORD BY 16-BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD4701AC-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4702C-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4702G-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| uPD4704C(A) | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4711AGS | 制造商:Panasonic Industrial Company 功能描述:IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。