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參數(shù)資料
| 型號： | UPD46128953-E15X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍 |
| 文件頁數(shù)： | 26/60頁 |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-E15X |
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Preliminary Data Sheet M17506EJ1V1DS
26
μ
PD46128953-X
4. 1. 5
Function mode
The burst read mode is set by this item. If 0 is input to A/DQ5 in the 5th cycle, the burst mode is set.
Be sure to input 0 to A/DQ5.
4. 1. 6
Driver strength
The output driver strength is set by this item. If 00 are input to A/DQ7 and A/DQ6 in the 5th cycle, the output driver
strength is set to Strong. If 11 are input to A/DQ7 and A/DQ6 in the 5th cycle, the output driver strength is set to Middle.
If 10 are input to A/DQ7 and A/DQ6 in the 5th cycle, the output driver strength is set to Weak.
4. 1. 7
Read Latency
The read latency count is set by this item. If 100 are input to A/DQ2, A/DQ1, and A/DQ0 in the 6th cycle, the read
latency is set to 6. If 101 are input to A/DQ2, A/DQ1, and A/DQ0 in the 6th cycle, the read latency is set to 7. If 110 are
input to A/DQ2, A/DQ1, and A/DQ0 in the 6th cycle, the read latency is set to 8. Write latency is automatically set RL-1.
4. 1. 8
Single Write
The write mode is set by this item, if 0 is input to A/DQ4 in the 6th cycle, the write mode is set to burst write.
Be sure to input 0 to A/DQ4.
4. 1. 9
Valid Clock Edge
The valid clock edge (Rising edge or Falling edge) is set in the burst mode. If 1 is input to A/DQ5 in the 6th cycle,
rising edge is set to valid clock edge.
4. 1. 10
Reset to Asynchronous
This function is not available now and reserved for future function. Be sure to input 1 to A/DQ6.
4. 1. 11
/WE control
The input timing of /WE is set by this item. If 0 is input to A/DQ7 in the 6th cycle, the input timing of /WE is set to be
the same as the timing of loading an address (/WE = LOW while /ADV = LOW). Refer to
5.3 Loading Command
(read/write)
.
Be sure to input 0 to A/DQ7.
4. 1. 12
Setting of unused bits
Some of the undefined bits are used to enter a test mode that is not disclosed. Therefore, be sure to input 1 to the
undefined bits (A/DQ21 to A/DQ1 and DQ31 to DQ22 in the 4th cycle, A/DQ21 to A/DQ8 and DQ31 to DQ22 in the 5th
cycle, and A/DQ3, A/DQ21 to A/DQ8, and DQ31 to DQ22 in the 6th cycle).
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