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參數(shù)資料
| 型號： | UPD46128953-E15X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動(dòng)指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍 |
| 文件頁數(shù)： | 5/60頁 |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-E15X |
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Preliminary Data Sheet M17506EJ1V1DS
5
μ
PD46128953-X
(2/2)
Symbol
Description
DM0 to DM3
Synchronous write data mask input.
These signals can mask write data during burst write.
To input data mask, the setup time and hold time must be satisfied at the rising edge of CLK.
Data mask can be controlled in byte units.
DM0: A/DQ0 to ADQ7
DM1: A/DQ8 to ADQ15
DM2: A/DQ16 to ADQ21, DQ22 to DQ23
DM3: DQ24 to DQ31
Synchronous wait output.
/WAIT is a status signal (output) that indicates the preparation for starting burst read/burst write
This pin outputs a LOW while the internal circuit is busy, and a HIGH when it is ready.
The wait signal is output at the rising edge of CLK.
Supply voltage:
Usually, the supply voltage is 1.85 V. Refer to
DC Characteristics and Recommended Operation
Conditions
.
Supply voltage:
Ground
Supply voltage:
Supply voltage for DQ. Usually, this voltage is 1.85 V. Refer to
DC Characteristics and Recommended
Operation Conditions
.
Supply voltage:
Ground for DQ.
No connection
Some signals can be applied because this pin is not internally connected.
/WAIT
V
DD
V
SS
V
DD
Q
V
SS
Q
NC
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