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參數(shù)資料
| 型號： | UPD46128953-X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍 |
| 文件頁數(shù)： | 13/60頁 |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-X |
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Preliminary Data Sheet M17506EJ1V1DS
13
μ
PD46128953-X
3. Burst Operation
3. 1 Features of Burst Operation
Function
Features
Burst Length
8 double words
Burst Wrap
Wrap
Burst Sequence
Linear
Valid Clock Edge
CLK Rising Edge
Latency Count
Read Latency
6, 7, 8
Write Latency
5, 6, 7
3. 2 Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through Mode Register Set sequence after power-up. Once
RL is set through Mode Register Set sequence, write latency, that is the number of clock cycles between address being
latched and first write data being latched, is automatically set to RL
1.
Latency Count
Grade
Clock Frequency
Read Latency
Write Latency
Note
-E12X
<83 MHz
7, 8
6, 7
-E15X
<66 MHz
6, 7, 8
5, 6, 7
Note
Write Latency = Read Latency
1
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