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參數(shù)資料
| 型號： | UPD46128953-X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍 |
| 文件頁數(shù)： | 7/60頁 |
| 文件大小： | 468K |
| 代理商： | UPD46128953-X |
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Preliminary Data Sheet M17506EJ1V1DS
7
μ
PD46128953-X
Truth Table
Mode
/CE1
CE2
CLK
/ADV
/OE
/WE
A/DQ0-A/DQ21 , DQ22-DQ31
Deselect (Standby Mode 1)
H
H
×
×
×
High-Z
Power Down (Standby Mode 2)
Note1
×
L
×
×
×
×
High-Z
Output Disable
L
H
×
H
×
High-Z
Start Address Latch
Note2
L
H
×
High-Z
Start Address not Latch
Note3
H
×
×
Low-Z or High-Z
Read Command input
Note2
L
H
H
High-Z
Write Command input
Note2
L
H
L
High-Z
Burst Read Termination
Note4
L to H
×
×
×
Low-Z to High-Z
Burst Write Termination
Note4
×
×
×
High-Z
Notes 1.
CE2 pin must be fixed HIGH except Standby Mode 2 (refer to
2.3 Standby Mode Status Transition
).
2.
Start address latch and read/write command input are performed at the next rising edge of clock when /ADV
is transferred HIGH to LOW.
3.
It is impossible that Start address latch and read/write command input are performed at the first rising edge
of clock during /ADV is fixed HIGH.
4.
Refer to
3.6 Burst Read Termination
,
3.7 Burst Write Termination
.
Remark
H, HIGH: V
IH
, L, LOW: V
IL
,
×
: V
IH
or V
IL
For read/write operation, refer to
7 Timing Charts.
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