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參數(shù)資料
| 型號(hào)： | UPD70216HLP-20 |
| 廠商： | NEC Corp. |
| 英文描述： | V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR |
| 中文描述： | V40HLTM，V50HLTM 16 / 8，16位微處理器 |
| 文件頁數(shù)： | 34/110頁 |
| 文件大小： | 625K |
| 代理商： | UPD70216HLP-20 |
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34
μ
PD70208H, 70216H
Data Sheet U13225EJ4V0DS00
13. STANDBY FUNCTIONS
The V40HL and V50HL have two modes, the HALT mode and STOP mode, as standby functions.
(1)
HALT mode
When the HALT instruction is executed, the clock to internal CPU circuitry (excluding the HALT mode release circuit)
is stopped.
(2)
STOP mode
When the HALT instruction is executed, all clocks to the CPU and internal I/Os are stopped.
STOP mode should be used when a resonator is connected to the X1 and X2 pins.
Remark
Switching between HALT mode and STOP mode is performed by setting a system I/O area register.
14. RESET OPERATION
When the RESET pin is driven low and this level is held for 4 clock cycles or more from the fall of the signal, the CPU
and on-chip peripheral LSIs are reset.
When the RESET pin subsequently returns to the high level, the CPU begins an instruction prefetch from address
FFFF0H.
When the V40HL and V50HL are reset, its status is fully compatible with the V40 and V50.
Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved
area.
Table 14-1 shows the main statuses of the on-chip peripheral LSIs when a reset is performed.
Table 14-1. Main Statuses of On-Chip Peripheral LSIs After Reset
Memory, external I/O, DMA & refresh
Upper & lower memory blocks
: 3-wait insertion
: set to 512 KB
Refresh cycle
Refresh enabling/disabling
: set to 72 clock cycles
: not affected by reset
Baud rate
Character
Parity
Stop bits
Break detection
: x 64
: 7 bits
: None
: 1 bit
: None
μ
PD71071 mode
Demand mode
Auto initialization disabled
Verify transfer, byte transfer
Bus release mode
DMA enabled
DMAU
SCU
REFU
WCU
Caution When a reset is performed, the SCU, TCU, ICU and DMAU cannot be used.
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