4
μ
P
D
AC CY V
P
S
Z
Instruc-
tion
Group
Mnemonic
Operand(s)
Bytes
Operation
Operation Code
Flags
7 6 5 4 3 2 1 0
0 1 1 0 0 1 0 1
0 1 1 0 0 1 0 0
1 1 1 1 0 0 1 1
1 1 1 1 0 0 1 0
1 0 1 0 0 1 0 W
1 0 1 0 0 1 1 W
1 0 1 0 1 1 1 W
1 0 1 0 1 1 0 W
1 0 1 0 1 0 1 W
1
1
1
1
1
1
1
1
1
7 6 5 4 3 2 1 0
×
×
×
×
×
×
×
×
×
×
×
×
2
2
2
2
See
Table
15-8
See
Table
15-8
See
Table
15-8
See
Table
15-8
See
Table
15-8
R
P
REPC
REPNC
REP
REPE
REPZ
REPNE
REPNZ
MOVBK
CMPBK
CMPM
LDM
STM
dst-block,
src-block
src-block,
dst-block
dst-block
src-block
dst-block
Clock Cycles
2
2
2
2
See
Table
15-9
See
Table
15-9
See
Table
15-9
See
Table
15-9
See
Table
15-9
V40HL V50HL
While CW
≠
0, the following byte primitive block transfer
instruction is executed and CW is decremented (–1).
If there is a pending interrupt, it is serviced.
If CY
≠
1 the loop is exited.
Same as above
If CY
≠
0 the loop is exited.
While CW
≠
0, the following byte primitive block transfer
instruction is executed and CW is decremented (–1).
If there is a pending interrupt, it is serviced.
If the primitive block transfer instruction is CMPBK or
CMPM and Z
≠
1 the loop is exited.
Same as above
If Z
≠
0 the loop is exited.
If W = 0: (IY)
←
(IX)
DIR = 0 : IX
←
IX + 1, IY
←
IY + 1
DIR = 1 : IX
←
IX – 1, IY
←
IY – 1
If W = 1: (IY + 1, IY)
←
(IX + 1, IX)
DIR = 0 : IX
←
IX + 2, IY
←
IY + 2
DIR = 1 : IX
←
IX – 2, IY
←
IY – 2
If W = 0: (IX) – (IY)
DIR = 0 : IX
←
IX + 1, IY
←
IY + 1
DIR = 1 : IX
←
IX – 1, IY
←
IY – 1
If W = 1: (IX + 1, IX) – (IY + 1, IY)
DIR = 0 : IX
←
IX + 2, IY
←
IY + 2
DIR = 1 : IX
←
IX – 2, IY
←
IY – 2
If W = 0: AL – (IY)
DIR = 0 : IY
←
IY + 1; DIR = 1 : IY
←
IY – 1
If W = 1: AW – (IY + 1, IY)
DIR = 0 : IY
←
IY + 2; DIR = 1 : IY
←
IY – 2
If W = 0: AL
←
(IX)
DIR = 0 : IX
←
IX + 1; DIR = 1 : IX
←
IX – 1
If W = 1: AW
←
(IX + 1, IX)
DIR = 0 : IX + 2; DIR = 1 : IX
←
IX – 2
If W = 0: (IY)
←
AL
DIR = 0 : IY
←
IY + 1; DIR = 1 : IY
←
IY – 1
If W = 1: (IY + 1, IY)
←
AW
DIR = 0 : IY
←
IY + 2; DIR = 1 : IY
←
IY – 2