參數(shù)資料
型號： UPD703100A-40
廠商： NEC Corp.
英文描述： V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù)： 111/132頁
文件大?。?/td> 1174K
代理商： UPD703100A-40
Preliminary Data Sheet U14168EJ2V0DS00
111
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page)
→
external I/O transfer) (3/3)
Remarks 1.
This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2.
The broken lines indicate high impedance.
3.
n = 0 to 7, m = 0 to 3
TRPW
T1
TRHW
T2
TDAW
TW
T3
TCPW
TO1
TO2
TW
TDAW
<56>
<57>
<58>
<59>
<76>
<61>
<60>
<94>
<64>
<77>
<65>
<83>
<63>
<81>
<67>
<66>
<71>
<82>
<96>
<105>
<68>
<69>
<70>
<79>
<48>
<97>
<106>
<42>
<41>
<50>
<43>
<78>
<37>
<24>
<25>
<24>
<25>
<25>
<24>
Data
Data
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
UCAS (Output)
LCAS (Output)
RD (Output)
OE (Output)
DMAAKm (Output)
WE (Output)
IORD (Output)
IOWR (Output)
D0 to D15 (I/O)
WAIT (Input)
BCYST (Output)
Row address
Column address
Column address
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