參數(shù)資料
型號: UPD703100A-40
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù): 76/132頁
文件大?。?/td> 1174K
代理商: UPD703100A-40
Preliminary Data Sheet U14168EJ2V0DS00
76
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
Load Condition
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert
a buffer or other element to reduce the device's load capacitance to 50 pF or lower.
(1) Clock timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
μ
PD703100A-40
12.5
250
ns
μ
PD703100A-33
15
250
ns
Direct
mode
μ
PD703101A-33,
μ
PD 703102A-33,
15
50
ns
μ
PD703100A-40
125
250
ns
X1 input cycle
<1>
t
CYX
PLL mode
μ
PD703100A-33,
703101A-33,
703102-A33
150
250
ns
Direct mode
5
ns
X1 input high-level width
<2>
t
WXH
PLL mode
50
ns
Direct mode
5
ns
X1 input low-level width
<3>
t
WXL
PLL mode
50
ns
Direct mode
4
ns
X1 input rise time
<4>
t
XR
PLL mode
10
ns
X1 input fall time
<5>
t
XF
Direct mode
4
ns
PLL mode
10
ns
μ
PD703100A-40
2
40
MHz
μ
PD703100A-33
2
33
MHz
CPU operating frequency
φ
μ
PD703101A-33, 703102A-33
10
33
MHz
μ
PD703100A-40
25
500
ns
μ
PD703100A-33
30
500
ns
CLKOUT output cycle
<6>
t
CYK
μ
PD703101A-33, 703102A-33
30
100
ns
CLKOUT input high-level width
<7>
t
WKH
0.5T – 7
ns
CLKOUT input low-level width
<8>
t
WKL
0.5T – 4
ns
CLKOUT input rise time
<9>
t
KR
5
ns
CLKOUT input fall time
<10>
t
KF
5
ns
Remark
T = t
CYK
C
L
= 50 pF
DUT
(Measured device)
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