參數(shù)資料
型號(hào)： UPD703100A-40
廠商： NEC Corp.
英文描述： V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù)： 82/132頁
文件大?。?/td> 1174K
代理商： UPD703100A-40
Preliminary Data Sheet U14168EJ2V0DS00
82
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(b) Read timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to address)
<30>
t
SAID
(1.5 + w
D
+ w) T – 20
ns
Data input setup time (to RD)
<31>
t
SRDID
(1 + w
D
+ w) T – 24
ns
RD, IORD low-level width
<32>
t
WRDL
(1 + w
D
+ w) T – 10
ns
RD, IORD high-level width
<33>
t
WRDH
T – 10
ns
RD, IORD
↓
delay time from address,
CSn
<34>
t
DARD
0.5T – 10
ns
Address delay time from RD, IORD
↑
<35>
t
DRDA
(0.5 + i) T – 5
ns
Data input hold time (from RD, IORD
↑
)
<36>
t
HRDID
0
ns
Data output delay time from RD, IORD
↑
<37>
t
DRDOD
(0.5 + i) T – 10
ns
WAIT setup time (to address)
<38>
t
SAW
Note
T – 20
ns
WAIT setup time (to BCYST
↓
)
<39>
t
SBSW
Note
T – 20
ns
WAIT hold time (to BCYST
↑
)
<40>
t
HBSW
Note
0
ns
Note
For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1.
T = t
CYK
2.
w: the number of waits due to WAIT.
3.
w
D
: the number of waits due to the DWC1 and DWC2 registers.
4.
i: the number of idle states that are inserted when a write cycle follows a read cycle.
5.
Maintain at least one of the data input hold times t
HKID
and t
HRDID
.
6.
n = 0 to 7
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