參數(shù)資料
型號(hào): UPD703100A-40
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù): 62/132頁
文件大?。?/td> 1174K
代理商: UPD703100A-40
Preliminary Data Sheet U14168EJ2V0DS00
62
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(3/7)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY
OV
S
Z
SAT
rr r r r 1 1 1 1 0 b R R R RR
dd d d d d d d d d d d d d d1
LD.BU
disp16[reg1],reg2
Notes 8, 10
adr
GR[reg1]+sign-extend(disp16)
GR[reg2]
zero-extend(Load-memory
(adr,Byte))
1
1
n
Note 11
rr r r r 1 1 1 0 0 1 R R R RR
dd d d d d d d d d d d d d d0
LD.H
disp16[reg1],reg2
Note 8
adr
GR[reg1]+sign-extend(disp16)
GR[reg2]
sign-extend(Load-memory
(adr,Half-word))
1
1
n
Note 9
rr r r r 1 1 1 1 1 1 R R R RR
dd d d d d d d d d d d d d d1
LD.HU
disp16[reg1],reg2
Note 8
adr
GR[reg1]+sign-extend(disp16)
GR[reg2]
zero-extend(Load-memory
(adr,Half-word))
1
1
n
Note 11
rr r r r 1 1 1 0 0 1 R R R RR
dd d d d d d d d d d d d d d1
LD.W
disp16[reg1],reg2
Note 8
adr
GR[reg1]+sign-extend(disp16)
GR[reg2]
Load-memory(adr,Word)
1
1
n
Note 9
rr r r r 1 1 1 1 1 1 R R R RR
00 0 0 0 0 0 0 0 0 1 0 0 0 00
Other than
regID=PSW
LDSR
reg2,regID
Note 12
SR[regID]
GR[reg2]
regID=PSW
1
1
1
×
×
×
×
×
reg1,reg2
rr r r r 0 0 0 0 0 0 R R R RR
GR[reg2]
GR[reg1]
1
1
1
imm5,reg2
rr r r r 0 1 0 0 0 0 i i i ii
GR[reg2]
sign-extend(imm5)
1
1
1
00 0 0 0 1 1 0 0 0 1 R R R RR
ii i i i i i i i i i i i i ii
MOV
imm32,reg1
ii i i i i i i i i i i i i ii
GR[reg1]
imm32
2
2
2
rr r r r 1 1 0 0 0 1 R R R RR
MOVEA
imm16,reg1,reg2
ii i i i i i i i i i i i i ii
GR[reg2]
GR[reg1]+ sign-extend(imm16)
1
1
1
rr r r r 1 1 0 0 1 0 R R R RR
MOVHI
imm16,reg1,reg2
ii i i i i i i i i i i i i ii
GR[reg2]
GR[reg1]+(imm16 II 0
16
)
1
1
1
rr r r r 1 1 1 1 1 1 R R R RR
reg1,reg2,reg3
ww w w w 0 1 0 0 0 1 0 0 0 00
GR[reg3] II GR[reg2]
GR[reg2]
×
GR[reg1]
1
2
Note 14
2
rr r r r 1 1 1 1 1 1 i i i ii
MUL
imm9,reg2,reg3
w w w w w 0 1 0 0 1 1 1 1 1 00
GR[reg3] II GR[reg2]
GR[reg2]
×
sign-
extend(imm9)
Note 13
1
2
Note 14
2
reg1,reg2
rr r r r 0 0 0 1 1 1 R R R RR
GR[reg2]
GR[reg2]
Note 6
×
GR[reg1]
Note 6
1
1
2
MULH
imm5,reg2
rr r r r 0 1 0 1 1 1 i i i ii
GR[reg2]
GR[reg2]
Note 6
×
sign-extend (imm5)
1
1
2
rr r r r 1 1 0 1 1 R R R R RR
MULHI
imm16,reg1,reg2
ii i i i i i i i i i i i i ii
GR[reg2]
GR[reg1]
Note 6
×
imm16
1
1
2
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