參數(shù)資料
型號: UPD703100AF1-40-FA1
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù): 124/132頁
文件大?。?/td> 1174K
代理商: UPD703100AF1-40-FA1
Preliminary Data Sheet U14168EJ2V0DS00
124
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(12) CSI0 to CSI3 timing
(a) Master mode
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<147>
t
CYSK1
Output
100
ns
SCKn high-level width
<148>
t
WSK1H
Output
0.5t
CYSK1
– 20
ns
SCKn low-level width
<149>
t
WSK1L
Output
0.5t
CYSK1
– 20
ns
SIn setup time (to SCKn
)
<150>
t
SSISK
30
ns
SIn hold time (from SCKn
)
<151>
t
HSKSI
0
ns
SOn output delay time (from SCKn
)
<152>
t
DSKSO
20
ns
SOn output hold time (from SCKn
)
<153>
t
HSKSO
0.5t
CYSK1
– 5
ns
Remark
n = 0 to 3
(b) Slave mode
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<147>
t
CYSK1
Input
100
ns
SCKn high-level width
<148>
t
WSK1H
Input
30
ns
SCKn low-level width
<149>
t
WSK1L
Input
30
ns
SIn setup time (to SCKn
)
<150>
t
SSISK
10
ns
SIn hold time (from SCKn
)
<151>
t
HSKSI
10
ns
SOn output delay time (from SCKn
)
<152>
t
DSKSO
30
ns
SOn output hold time (from SCKn
)
<153>
t
HSKSO
t
WSK1H
ns
Remark
n = 0 to 3
SCKn (I/O)
<149>
<147>
<148>
Sln (Input)
<150>
<151>
Input data
SOn (Output)
<152>
Output data
<153>
Remarks 1.
The broken lines indicate high impedance.
2.
n = 0 to 3
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