參數(shù)資料
型號： UPD703100AF1-40-FA1
廠商： NEC Corp.
英文描述： V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù)： 35/132頁
文件大小： 1174K
代理商： UPD703100AF1-40-FA1
Preliminary Data Sheet U14168EJ2V0DS00
35
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
Table 8-1. List of Interrupts (3/3)
Interrupt/Exception Source
Type
Category
Name
Control
Register
Generation Source
Generating
Unit
Default
Priority
Exception
Code
Handler
Address
Restore
PC
Interrupt
INTSR0
SRIC0
UART0 receive
completion
SIO
38
0320H
00000320H
nextPC
Interrupt
INTST0
STIC0
UART0 send
completion
SIO
39
0330H
00000330H
nextPC
Interrupt
INTCSI1
CSIC1
CSI1 send/receive
completion
SIO
40
0340H
00000340H
nextPC
Interrupt
INTSER1
SEIC1
UART1 receive error
SIO
41
0350H
00000350H
nextPC
Interrupt
INTSR1
SRIC1
UART1 receive
completion
SIO
42
0360H
00000360H
nextPC
Interrupt
INTST1
STIC1
UART1 send
completion
SIO
43
0370H
00000370H
nextPC
Interrupt
INTCSI2
CSIC2
CSI2 send/receive
completion
SIO
44
0380H
00000380H
nextPC
Interrupt
INTCSI3
CSIC3
CSI3 send/receive
completion
SIO
45
03C0H
000003C0H
nextPC
Maskable
Interrupt
INTAD
ADIC
A/D conversion
completion
ADC
46
0400H
00000400H
nextPC
Remarks 1.
Default priority: The priority that takes precedence when two or more maskable interrupt requests
having the same priority level are generated at the same time. The highest priority
is 0.
Restore PC: The PC value that is saved in EIPC or FEPC when the interrupt or exception
processing is started. However, the restore PC value that is saved when an interrupt is
acknowledged during the execution of a division instruction (DIV, DIVH, DIVU, or
DIVHU) is the PC value of the current instruction (DIV, DIVH, DIVU, or DIVHU).
2.
The execution address of the illegal instruction when an illegal opcode exception occurs is obtained
according to the calculation “restore PC - 4.”
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