參數(shù)資料
型號(hào): UPD703100AF1-40-FA1
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁(yè)數(shù): 86/132頁(yè)
文件大?。?/td> 1174K
代理商: UPD703100AF1-40-FA1
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Preliminary Data Sheet U14168EJ2V0DS00
86
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(d) DMA flyby transfer timing (SRAM
external I/O transfer) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT
)
<24>
t
SWK
10
ns
WAIT hold time (from CLKOUT
)
<25>
t
HKW
2
ns
RD low-level width
<32>
t
WRDL
(1 + w
D
+ w
F
+ w)
T –
10
ns
RD high-level width
<33>
t
WRDH
T – 10
ns
RD
delay time from address, CSn
<34>
t
DARD
0.5T – 5
ns
Address delay time from RD
<35>
t
DRDA
(0.5 + i) T – 5
ns
Data output delay time from RD
<37>
t
DRDOD
(0.5 + i) T – 10
ns
WAIT setup time (to address)
<38>
t
SAW
Note
T – 20
ns
WAIT setup time (to BCYST
)
<39>
t
SBSW
Note
T – 20
ns
WAIT hold time (from BCYST
)
<40>
t
HBSW
Note
0
ns
IOWR
delay time from address
<41>
t
DAWR
0.5T – 5
ns
Address setup time (to IOWR
)
<42>
t
SAWR
(1.5 + w
D
+ w) T – 10
ns
Address delay time from UWR, LWR,
IOWR
<43>
t
DWRA
0.5T – 5
ns
IOWR high-level width
<44>
t
WWRH
T – 10
ns
IOWR low-level width
<45>
t
WWRL
(1 + w
D
+ w) T – 10
ns
w
F
= 0
0
ns
RD
delay time from IOWR
<48>
t
DWRRD
w
F
= 1
T – 10
ns
IOWR
delay time from DMAAKm
<49>
t
DDAWR
0.5T – 10
ns
DMAAKm
delay time from IOWR
<50>
t
DWRDA
(0.5 + w
F
) T – 10
ns
Note
For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1.
T = t
CYK
2.
w: the number of waits due to WAIT.
3.
w
D
: the number of waits due to the DWC1 and DWC2 registers.
4.
w
F
: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5.
i: the number of idle states that are inserted when a write cycle follows a read cycle.
6.
n = 0 to 7, m = 0 to 3
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