參數(shù)資料
型號： UPD703100AF1-40-FA1
廠商： NEC Corp.
英文描述： V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù)： 96/132頁
文件大?。?/td> 1174K
代理商： UPD703100AF1-40-FA1
Preliminary Data Sheet U14168EJ2V0DS00
96
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(b) Read timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to CLKOUT
↑
)
<26>
t
SKID
10
ns
Data input hold time (from CLKOUT
↑
)
<27>
t
HKID
2
ns
Data output delay time from OE
↑
<37>
t
DRDOD
(0.5 + i) T – 10
ns
Column address setup time
<58>
t
ASC
(0.5 + w
CP
) T – 10
ns
Column address hold time
<59>
t
CAH
(1.5 + w
DA
) T – 10
ns
RAS hold time
<63>
t
RSH
(1.5 + w
DA
) T – 10
ns
Column address read time for RAS
<64>
t
RAL
(2 + w
CP
+ w
DA
) T – 10
ns
CAS pulse width
<65>
t
CAS
(1 + w
DA
) T – 10
ns
WE setup time (to CAS
↓
)
<68>
t
RCS
(1 + w
CP
) T – 10
ns
WE hold time (from RAS
↑
)
<69>
t
RRH
0.5T – 10
ns
WE hold time (from CAS
↑
)
<70>
t
RCH
T – 10
ns
Output enable access time
<72>
t
OEA
(1 + w
CP
+ w
DA
) T – 20
ns
Access time from column address
<74>
t
AA
(1.5 + w
CP
+ w
DA
)
T –
20
ns
CAS access time
<75>
t
CAC
(1 + w
DA
) T – 20
ns
Output buffer turn-off delay time (from
OE
↑
)
<78>
t
OEZ
0
ns
Output buffer turn-off delay time (from
CAS
↑
)
<79>
t
OFF
0
ns
Access time from CAS precharge
<80>
t
ACP
(2 + w
CP
+ w
DA
) T – 20
ns
CAS precharge time
<81>
t
CP
(1 + w
CP
) T – 5
ns
High-speed page mode cycle time
<82>
t
PC
(2 + w
CP
+ w
DA
) T – 10
ns
RAS hold time for CAS precharge
<83>
t
RHCP
(2.5 + w
CP
+ w
DA
)
T –
10
ns
Remarks 1.
T = t
CYK
2.
w
CP
: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
w
DA
: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
i: the number of idle states that are inserted when a write cycle follows a read cycle.
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