
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User
’
s Manual U15862EJ3V0UD
358
8.4.2 Operation as external event counter (8 bits)
The external event counter counts the number of clock pulses input to the TI5n pin from an external source by
using 8-bit timer counter 5n (TM5n).
Each time the valid edge specified by timer clock selection register 5n (TCL5n) is input to the TI5n pin, the TM5n
register is incremented. Either the rising edge or the falling edge can be specified as the valid edge.
When the count value of the TM5n register matches the value of 8-bit timer compare register 5n (CR5n), the TM5n
register is cleared to 0 and an interrupt request signal (INTTM5n) is generated.
Setting method
<1>
Set each register.
TCL5n register:
Selects the TI5n input edge.
Falling edge of TI5n pin
→
TLC5n = 00H
Rising edge of TI5n pin
→
TCL5n = 01H
Compare value (N)
CR5n register:
TMC5n register: Stops count operation, selects the mode in which clear & start occurs on a match
between the TM5n register and CR5n register, disables timer output F/F inversion
operation, and disables timer output.
(TMC5n register = 0000xx00B,
×
: don
’
t care)
When the TCE5n bit of the TMC5n register is set to 1, the counter counts the number of pulses input from
TI5n.
When the values of the TM5n register and CR5n register match, INTTM5n is generated (TM5n register is
cleared to 00H).
Then, INTTM5n is generated each time the values of the TM5n register and CR5n register match.
<2>
<3>
<4>
INTTM5n is generated when the valid edge of TI5n is input N + 1 times: N = 00H to FFH
Caution
During external event counter operation, do not rewrite the value of the CR5n register.
Remark
n = 0, 1
Figure 8-3. Timing of External Event Counter Operation (with Rising Edge Specified)
00H
01H
02H
03H
04H
05H
N
–
1
N
N
00H
01H
02H
03H
TI5n
CR5n
INTTM5n
TCE5n
TM5n count value
Count start
Remark
n = 0, 1