參數(shù)資料
型號(hào): UPD720130
廠商: NEC Corp.
英文描述: USB2.0 to IDE Bridge
中文描述: USB2.0轉(zhuǎn)IDE橋
文件頁數(shù): 17/44頁
文件大?。?/td> 316K
代理商: UPD720130
Data Sheet S16302EJ3V0DS
17
μ
PD720130
3.3
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
V
DD33
V
DD25
3.3 V power supply rail
2.5 V power supply rail
0.5 to
+
4.6
0.5 to
+
3.6
V
V
Input voltage, 5 V buffer
V
I
3.0 V
V
DD33
3.6 V
V
I
<
V
DD33
+
3.0 V
0.5 to
+
6.6
V
Input voltage, 3.3 V buffer
V
I
3.0 V
V
DD33
3.6 V
V
I
<
V
DD33
+
1.0 V
0.5 to
+
4.6
V
Input voltage, 2.5 V buffer
V
I
2.3 V
V
DD25
2.7 V
V
I
<
V
DD25
+
0.9 V
0.5 to
+
3.6
V
Output voltage, 5 V buffer
V
O
3.0 V
V
DD33
3.6 V
V
O
<
V
DD33
+
3.0 V
0.5 to
+
6.6
V
Output voltage, 3.3 V buffer
V
O
3.0 V
V
DD33
3.6 V
V
O
<
V
DD33
+
1.0 V
0.5 to
+
4.6
V
Output voltage, 2.5 V buffer
V
O
2.3 V
V
DD25
2.7 V
V
O
<
V
DD25
+
0.9 V
0.5 to
+
3.6
V
Output current, 5 V buffer
I
O
I
OL
= 6 mA
20
mA
Output current, 3.3 V buffer
I
O
I
OL
= 6 mA
I
OL
= 3 mA
20
10
mA
mA
Operating ambient temperature
T
A
0 to
+
70
°
C
Storage temperature
T
stg
65 to
+
150
°
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameters. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent the
quality assurance range during normal operation.
Two Power Supply Rails Limitation
The
μ
PD720130 has two power supply rails (2.5 V, 3.3 V). The system will require the time when power supply
rail is stable at V
DD
level. And, there will be difference between the time of V
DD25
and V
DD33
. The
μ
PD720130
requires that V
DD25
should be stable before V
DD33
becomes stable. At this case, the system must ensure that the
absolute maximum ratings for V
I
/ V
O
are not exceeded. System reset signaling should be asserted more than
specified time after both V
DD25
and V
DD33
are stable.
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