參數(shù)資料
型號： UPD720130
廠商： NEC Corp.
英文描述： USB2.0 to IDE Bridge
中文描述： USB2.0轉(zhuǎn)IDE橋
文件頁數(shù)： 24/44頁
文件大小： 316K
代理商： UPD720130
Data Sheet S16302EJ3V0DS
24
μ
PD720130
AC Characteristics (V
DD33
= 3.0 to 3.6 V, V
DD25
= 2.3 to 2.7 V, T
A
= 0 to
+
70
°
C)
System Clock Ratings
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
X
’
tal
500
ppm
30
+
500
ppm
MHz
Clock frequency
f
CLK
Oscillator block
500
ppm
30
+
500
ppm
MHz
Clock duty cycle
t
DUTY
45
50
55
%
Remarks 1.
Recommended accuracy of clock frequency is
±
100 ppm.
2.
Required accuracy of X
’
tal or Oscillator block is including initial frequency accuracy, the spread of
X
’
tal capacitor loading, supply voltage, temperature, and aging, etc.
System Reset signaling
Parameter
Symbol
Conditions
Min.
Max.
Unit
Reset active time
t
rst
2
μ
s
USB Interface Block
(1/2)
Parameter
Symbol
Conditions
Min.
Max.
Unit
Full-speed Source Electrical Characteristics
Rise time (10% - 90%)
t
FR
C
L
= 50 pF,
R
S
= 36
4
20
ns
Fall time (90% - 10%)
t
FF
C
L
= 50 pF,
R
S
= 36
4
20
ns
Differential rise and fall time matching
t
FRFM
(t
FR
/t
FF
)
90
111.11
%
Full-speed data rate for device which are
high-speed capable
t
FDRATHS
Average bit rate
11.9940
12.0060
Mbps
Frame interval
t
FRAME
0.9995
1.0005
ms
Consecutive frame interval jitter
t
RFI
No clock adjustment
42
ns
Source jitter total (including frequency
tolerance):
To next transition
For paired transitions
t
DJ1
t
DJ2
3.5
4.0
+
3.5
+
4.0
ns
ns
Source jitter for differential transition to
SE0 transition
t
FDEOP
2
+
5
ns
Receiver jitter:
To next transition
For paired transitions
t
JR1
t
JR2
18.5
9
+
18.5
+
9
ns
ns
Source SE0 interval of EOP
t
FEOPT
160
175
ns
Receiver SE0 interval of EOP
t
FEOPR
82
ns
Width of SE0 interval during differential
transition
t
FST
14
ns
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相關代理商/技術參數(shù)
參數(shù)描述
UPD720130GC-9EU-A 制造商:NEC Electronics Corporation 功能描述:BRIDGE USB TO IDE SMD TQFP100
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