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參數(shù)資料
| 型號(hào)： | UPD72042GT |
| 廠商： | NEC Corp. |
| 英文描述： | LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL |
| 中文描述： | LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制 |
| 文件頁(yè)數(shù)： | 25/92頁(yè) |
| 文件大?。?/td> | 373K |
| 代理商： | UPD72042GT |
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μ
PD72042
25
Data Sheet S14870EJ1V0DS00
3.2.2 Two-Wire Data Transfer (SEL = 0)
(1) Control mode
When the C/D input is set high, control mode is set to control data transfer. Data transfer control involves the
following processing.
1
Register address setting
2
Register read/write selection
Remark
After reset (RESET) cancellation, the state enabling writing to the register at address 0000B is set.
Caution In control mode, each data item is read every eighth clock pulse. (Data of less than eight clock
periods is ignored.)
C/D
SCK
SIO
A3
A2
A1
A0
R
/
W
×
×
×
(2) Data read mode
Note
SIO pin input state
SIO pin output state
Cautions 1. When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore,
the remaining bits of the byte cannot be read; at the next falling edge, a read operation is
performed starting from the next byte in the case of RBF, or from the first bit for other registers.
2. The SIO pin is a CMOS I/O pin. So, be careful to avoid an output collision between the SIO
pin and the microcomputer. Further, a pull-up resistor is required when N-ch open-drain
output of the microcomputer is used. Note that if the last output level is low upon the
termination of read mode, current will flow constantly.
C/D
SCK
SIO
Note
A3
A2
A1
A0
×
×
×
D7
D6
D5
D4
D3
D2
D1
D0
1
Serial clock counter
reset pointer
State
Control mode
(selection of register read)
Data read mode
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