- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383983 > UPD72042GT (NEC Corp.) LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL PDF資料下載
參數(shù)資料
| 型號： | UPD72042GT |
| 廠商： | NEC Corp. |
| 英文描述： | LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL |
| 中文描述： | LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制 |
| 文件頁數(shù)： | 40/92頁 |
| 文件大小： | 373K |
| 代理商： | UPD72042GT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
μ
PD72042
40
Data Sheet S14870EJ1V0DS00
FLG
Address
Read/write
When reset : 00000010B
: 0001B (1H)
: Read
Flag register
FLG is a one-byte read register used to indicate statuses such as the communication state, command execution
state, and interrupt state.
[MARQ]
1 : A request for communication as the master unit is being made.
0 : No request for communication as the master unit is being made. Data can be written to the SAR1, SAR2, and
MCR registers.
The MARQ flag is set and reset as described below.
Set
: When the CEX flag of the FLG register is set to 0 after 1000 or 1001 is set in COMC of the CMR register
Reset : When master communication is terminated
[STRQ]
1 : A request for slave unit data transmission is being made.
0 : No request for slave unit data transmission is being made.
The STRQ flag is set and reset as described below.
Set
: When the CEX flag of the FLG register is set to 0 after 1011 or 1100 is set in COMC of the CMR register
Reset : When slave data transmission is terminated
[SLRE]
1 : Slave reception or broadcast is allowed.
0 : Slave reception and broadcast are not allowed.
The SLRE flag is set and reset as described below.
Set
: When REEN of the CTR register is set to 1
Reset : When slave reception or broadcast reception is terminated normally or suspended, or when CEX of
the FLG register is set to 0 after 1111 is set in COMC of the CMR register
When SLRE = 0, bit 1 of the slave status is set to 1 regardless of the state of RBF; communication frame reception
based on the AH, BH, EH, and FH control bits, received from the master station, is not performed.
b7
—
b6
MARQ
b5
STRQ
b4
b3
b0
RAW
FLG
b2
b1
SLRE
CEX
STM
IRQ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| uPD72107GC-3B9 | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
| UPD72107 | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
| uPD72107CW | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
| uPD72107L | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
| UPD75008 | 4-BIT SINGLE-CHIP MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD72042GT(A) | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD720902AF5-667-JF2-E3-A | 功能描述:IC ADVANCED MEMORY BUFFER D1 RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:* 標(biāo)準(zhǔn)包裝:90 系列:- 應(yīng)用:PCI 至 PCI 橋 接口:PCI 電源電壓:3 V ~ 3.6 V 封裝/外殼:257-LFBGA 供應(yīng)商設(shè)備封裝:257-BGA MICROSTAR（16x16） 包裝:托盤 安裝類型:表面貼裝 產(chǎn)品目錄頁面:882 (CN2011-ZH PDF) 其它名稱:296-19316 |
| UPD72255YF1-GA5-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7225G | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD7225GB-3B7(A) | 制造商:Renesas Electronics Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。