- 您現在的位置：買賣IC網 > PDF目錄378746 > UPD7225G01 (NEC Corp.) PROGRAMMABLE LCD CONTROLLER/DRIVER PDF資料下載
參數資料
| 型號： | UPD7225G01 |
| 廠商： | NEC Corp. |
| 英文描述： | PROGRAMMABLE LCD CONTROLLER/DRIVER |
| 中文描述： | 可編程LCD控制器/驅動 |
| 文件頁數： | 17/52頁 |
| 文件大?。?/td> | 289K |
| 代理商： | UPD7225G01 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
Data Sheet S14308EJ6V0DS00
17
μ
PD7225
2.6 Blinking Data Memory
The blinking data memory stores blinking data used to control display on/off operation (blinking). Blinking
operation can be performed in segment units. Each bit in blinking data memory corresponds to a bit in the data
memory; if a bit in the blinking data memory is set to 1, the corresponding segment will blink.
The blinking data memory is addressed by the data pointer at the same time the data memory is addressed. Data
is written by using the WRITE BLINKING DATA MEMORY command, and bit manipulation can be performed by
using the AND BLINKING DATA MEMORY, or OR BLINKING DATA MEMORY command. The BLINKING ON
command is used to initiate blinking operation or select the blinking interval (refer to
3.2 Blinking Frequency
Setting
)
2.7 Display Data Latch
The display data latch stores the data of the 32
×
4-bit segment driver. Each bit of the display data latch
corresponds to a bit in the data memory. All contents of the data memory are transferred to the display data latch at
the rising edge of /CS, and the contents displayed on the LCD are modified. If blinking is set, the contents of data
memory are modified by the contents of blinking data memory and the resulting values are transferred to the display
data latch.
The display data written to the display data latch is successively selected by the control function performed by the
LCD timing control, and converted to segment drive signal before output.
2.8 LCD Driver
The LCD driver consists of the segment driver and the common driver, and generates the segment drive signal
and common drive signal.
The segment driver outputs a segment signal so that the relationship with the common drive signal is select level if
the drive data stored in the display data latch is 1. If the drive data stored in the display data latch is 0, the output of
the segment driver will be non-select level.
The common drive signal sequentially drives the LCD common poles according to the time divison specificaion.
2.9 LCD Timing Control
The LCD timing control generates the LCD drive timing according to the number of time divisions, the frequency
division ratio, and bias method, and supplies it to the LCD driver. In addition, the LCD timing control outputs a /SYNC
signal from the /SYNC pin in order to synchronize the display timing of each
μ
PD7225 when configured in a multi-
chip configuration.
In a multi-chip configuration, the common signal can be used in common or blinking operation can be
synchronized by making a wired-OR connection with the /SYNC pin of each
μ
PD7225.
相關PDF資料 |
PDF描述 |
|---|---|
| UPD7225G00 | PROGRAMMABLE LCD CONTROLLER/DRIVER |
| UPD7225GB-3B7 | PROGRAMMABLE LCD CONTROLLER/DRIVER |
| UPD7227 | CMOS, Intelligent, Dot-Matrix LCD Controller/Driver |
| UPD72852A | IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI |
| UPD72852AGB-8EU | IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI |
相關代理商/技術參數 |
參數描述 |
|---|---|
| UPD7225GB-3B7(A) | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD74HC04C | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD750068GT-396 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7507C189 | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD7508CU265 | 制造商:Panasonic Industrial Company 功能描述:IC |
發(fā)布緊急采購，3分鐘左右您將得到回復。