參數(shù)資料
型號(hào)： UPD7225G01
廠商： NEC Corp.
英文描述： PROGRAMMABLE LCD CONTROLLER/DRIVER
中文描述： 可編程LCD控制器/驅(qū)動(dòng)
文件頁(yè)數(shù)： 22/52頁(yè)
文件大?。?/td> 289K
代理商： UPD7225G01
Data Sheet S14308EJ6V0DS00
22
μ
PD7225
6.
RESET FUNCTION
When a low level of 12 clock cycles or more is input to the /RESET pin, the
μ
PD7225 will be reset to the following
conditions:
This condition is the same as when M2
M0 = 0, F1, F0 = 0 are executed by the MODE SET command.
Display data transfer from the data memory to the display data latch
This condition is the same as when
the UNSYNCHRONIZED TRANSFER command is executed.
Command/data register output
This condition is the same as when the WITHOUT SEGMENT DECODER
command is executed.
LCD display
This condition is the same as when the DISPLAY OFF or the BRINKING OFF command is
executed.
Function when the
μ
PD7225 is reset
S0-S31 and COM0-COM3 pins output V
DD
Serial data input
Disabled (/BUSY = 0) (However, /CS = 0)
When used in a multi-chip system, the reset state must be released (rising edge of /RESET) within 5
μ
s.
Figure 6-1. Reset Signal in Multi-Chip System
/RESET
0.7V
DD
0.3V
DD
12 clock cycles
5 s max.
μ
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