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參數(shù)資料
| 型號(hào)： | UPD7225GB-3B7 |
| 廠商： | NEC Corp. |
| 英文描述： | PROGRAMMABLE LCD CONTROLLER/DRIVER |
| 中文描述： | 可編程LCD控制器/驅(qū)動(dòng) |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 289K |
| 代理商： | UPD7225GB-3B7 |
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Data Sheet S14308EJ6V0DS00
15
μ
PD7225
(3) Divide-by-3 time division
The contents of the 8 bits of the serial register of the segment decoder output (8 bits) are written to bits 0, 1, and
2 of each address. In this case, 0 will be automatically written to bit 2 of address n + 2. For segment decoder
output, 0 will also be automatically written to bit 2 (D2) of address n.
bit3
bit0
0
D7 D6
D5 D4 D3
D2
0
D1 D0
n + 2
n + 1
Address n
The contents of bits 0, 1, and 2 of each address are effective as display data.
After the data is written, the data pointer points to address n + 3.
The segment decoder output written to the data memory corresponds to segments (a to g, DP) shown in Figure
2-1 as follows:
bit3
bit0
e
f
d
g
a
DP
c
b
n + 2
n + 1
Address n
(4) Divide-by-4 time division
The contents of the 8 bits of the serial register or the segment decoder output (8 bits) are written to bits 0, 1, 2,
and 3 of each address. For segment decoder output, 0 is automatically written to bit 3 (D3) of address n.
bit3
bit0
D7 D6 D5 D4
D3
0
D2 D1 D0
n + 1
Address n
The contents of all bits of each address are effective as display data.
After the data is written, the data pointer points to address n + 2.
When 7 segments are used, the segment decoder output written to the data memory corresponds to segments
(a to g, DP) shown in Figure 2-1 as follows:
bit3
bit0
d
e
g
f
DP
c
b
a
n + 1
Address n
When 14 segments are used, the segment decoder output is written to bits 0, 1, 2, and 3 of each address. In
this case, 0s are automatically written to bit 3 of address n + 2, and bit 0 of address n+ 1.
bit3
bit0
D15 D14 D13 D12
D11
0
D10 D9 D8
D7 D6 D5
D4
0
D3 D2 D1 D0
n + 3
n + 2
n + 1
Address n
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