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參數(shù)資料
| 型號： | UPD7225GB-3B7 |
| 廠商： | NEC Corp. |
| 英文描述： | PROGRAMMABLE LCD CONTROLLER/DRIVER |
| 中文描述： | 可編程LCD控制器/驅(qū)動 |
| 文件頁數(shù)： | 5/52頁 |
| 文件大?。?/td> | 289K |
| 代理商： | UPD7225GB-3B7 |
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Data Sheet S14308EJ6V0DS00
5
μ
PD7225
1.
PIN FUNCTIONS
1.1 SI (Serial Input)
……
Input
This pin is used for inputting serial data (commands/data). Data to be displayed as well as 19 deffernet
commands for controlling the operation of the
μ
PD7225 can be input to this pin.
1.2 /SCK (Serial Clock)
……
Input
This pin is used for inputting the shift clock for serial data (SI input). The content of the SI input is read into the
serial register at the rising edge of this clock one bit at a time. /SCK input is effective when /CS = 0 and /BUSY = 1.
If /BUSY = 0, this input is ignored. If /CS = 1, this signal is ignored regardless of the /BUSY status.
1.3 C, /D (Command/Data)
……
Input
This input indicates whether the signal input from the SI pin is a command or data. A low level indicates data; a
high level indicates a command.
1.4 /BUSY
……
Tri-state output
This is an active-low output pin that is used to control serial data input disable/enable. A low level disables serial
data input; a high level enables serial data input. This pin becomes high impedance when /CS = 1.
1.5 /CS (Chip Select)
……
Input
When /CS is changed from high level to low level, the SCK counter in the
μ
PD7225 is cleared and serial data
input is enabled. At the same time, the data pointer is initialized to address 0. When /CS is set to high level after
serial data is input, the contents of the data memory are transferred to the display latch and displayed on the LCD.
1.6 /SYNC (SYNChronous)
……
Input/Output
The /SYNC pin is used to make a wired-OR connection when the common pins are shared or when blinking
operation is synchronized in a multi-chip configuration.
When the
μ
PD7225 is reset (/RESET = 0), the /SYNC pin outputs the clock frequency (f
CL
) divided by four (refer to
Figure 1-1
), and synchronizes the system clock (f
CL
/4) of the
μ
PD7225. When the reset is released (/RESET =1), the
display timing of each
μ
PD7225 is synchronized with the common drive signal timing shown in Figure 1-2.
Figure 1-1. /SYNC Pin Status During Reset (/RESET = 0)
f
CL
/SYNC
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