參數(shù)資料
型號： UPD72852
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT
中文描述： 馬鞍山集成電路
文件頁數(shù)： 20/48頁
文件大?。?/td> 249K
代理商： UPD72852
Data Sheet S14920EJ3V0DS
20
μ
PD72852
4. PHY/LINK INTERFACE
4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface
The LPS pin monitors the On/Off status of the Link power state. This pin is used during the PHY/Link interface
Enable/Disable (initialization).
Reset
When the LPS input pin is Low for TLPS_RESET:
CTL0, CTL1 and D0-D7 output Low (When the isolation barrier is Hi-Z).
SCLK continuously supplies the clock signal to the Link.
Disable
When the LPS input pin is Low for TLPS_DISABLE:
CTL0, CTL1, D0-D7 continue to output Low as TLPS_RESET has already occurred (When the isolation barrier is Hi-Z).
SCLK to Link stops and it outputs Low (When the isolation barrier is Hi-Z).
Table 4-1. LPS Timing Parameters
Parameter
Symbol
MIN.
MAX.
Unit
LPS = Low propagation delay (with isolation barrier)
t
LPSL
0.09
1.00
μ
s
LPS = High propagation delay (with isolation barrier)
t
LPSH
0.09
1.00
μ
s
Reset active
t
LPS_RESET
1.2
2.75
μ
s
Disable active
t
LPS_DISABLE
25
30
μ
s
Setup time when using isolation barrier
t
RESTORE
15
20
μ
s
Figure 4-1. LPS Waveform when Connected to Isolation Barrier
t
LPSH
t
LPSL
相關(guān)PDF資料
PDF描述
UPD72852GB-8EU MOS INTEGRATED CIRCUIT
UPD72870F1 IEEE1394 1-CHIP OHCI HOST CONTROLLER
UPD72870FA2 IEEE1394 1-CHIP OHCI HOST CONTROLLER
UPD72871F1 IEEE1394 1-CHIP OHCI HOST CONTROLLER
UPD72871FA2 IEEE1394 1-CHIP OHCI HOST CONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD74HC04C 制造商:Panasonic Industrial Company 功能描述:IC
UPD750068GT-396 制造商:Renesas Electronics Corporation 功能描述:
UPD7507C189 制造商:Panasonic Industrial Company 功能描述:IC
UPD7508CU265 制造商:Panasonic Industrial Company 功能描述:IC
UPD75208 制造商:Panasonic Industrial Company 功能描述:IC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*