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參數(shù)資料
| 型號(hào)： | UPD72852GB-8EU |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 249K |
| 代理商： | UPD72852GB-8EU |
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Data Sheet S14920EJ3V0DS
19
μ
PD72852
3.4 PLL and Crystal Oscillation Circuit
3.4.1 Crystal Oscillation Circuit
To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm.
3.4.2 PLL
The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).
3.5 CMC
CMC shows the bus manager function which corresponds to the c bit of the Self_ID packet and the Contender bit
in the PHY register when the input is High.
The value of CMC can be changed with software through the Link layer; this pin sets the initial value during Power-
on Reset. Use a pull-up or pull-down resistor of 10 k
, based on the device’s specification.
3.6 PC0-PC2
The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to
Section 4.3.4.1 of the IEEE1394a-2000 specification for information regarding the Pwr_class. The value of Pwr can
be changed with software through the Link layer controller; this pin sets the initial value during Power-on Reset. Use
a pull-up or pull-down resistor of 10 k
based on the application.
3.7 RESETB
Connect an external capacitor of 0.1
μ
F between the RESETB pin and GND. If the voltage drops below 0 V, a
reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register.
3.8 RI1
Connect an external resistor of 9.1 k
between the RI1 pin and GND to limit the LSI’s current.
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