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參數(shù)資料
| 型號(hào)： | UPD72852GB-8EU |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 26/48頁 |
| 文件大小： | 249K |
| 代理商： | UPD72852GB-8EU |
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Data Sheet S14920EJ3V0DS
26
μ
PD72852
Table 4-11. PHY Operation Before LREQ Request to the CTL Function Changes
Request
State of CTL in C
B
after
LREQ was issued
Operation of the PHY
Fair, Priority
Receive
Hold the request if the acceleration of arbitration packet transmitted with
enable is 8 bits (ACK).
Except for 8 bits, the requests are ignored.
Ignore the request when the acceleration of arbitration is disabled.
Grant
Arbitration Won.
Idle, Status
Excluding when the bus reset is generated, Hold the requests.
Immediate
Grant
Receive
The packet is being transmitted to Link. Request Hold.
Idle, Status
Excluding when the bus reset is generated, hold the request.
Isochronous
Transmit Idle (driven by Link)
Request Hold.
Grant
Arbitration Won.
Receive
Request Hold.
Status
Request is ignored when sub-action gap is detected.
Idle
Register Read
Any (driven by Link)
Grant
Request Hold.
Receive
Request Hold.
Status
Hold the request until the corresponding register value is returned.
Idle
Register Write,
Acceleration
control
Any
Request is completed.
4.3.3 SCLK Timing
Table 4-12. SCLK Timing
Timing Constant
Comment
MIN.
MAX.
Unit
BUS_TO_LINK_DELAY
Period from receiving RX_DATA_PREFIX until
Receive to CTL is output.
2
9
SCLK cycle
DATA_PREFIX_TO_GRANT
Period when the Grant is output to CTL after
TX_DATA_PREFIX is output to a port.
25
SCLK cycle
LINK_TO_BUS_DELAY
Period when TX_DATA_END is output to all ports
after transmitting the packet by Link after idle was
asserted to CTL.
2
5
SCLK cycle
MAX_HOLD
Maximum period when Hold can be asserted by Link
to confirm Grant.
47
SCLK cycle
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