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參數(shù)資料
| 型號： | UPD72852GB-8EU |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 249K |
| 代理商： | UPD72852GB-8EU |
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Data Sheet S14920EJ3V0DS
21
μ
PD72852
Figure 4-2. PHY/Link Interface Reset and Disable
t
LPS_RESET
t
RESTORE
t
LPS_DISABLE
t
RESTORE
D, CTL, LREQ
LPS
LPS
(with isolation barrier)
SCLK
D, CTL, LREQ
LPS
LPS
(with isolation barrier)
SCLK
(a) Reset
(b) Disable
4.2 Link-on Indication
When the power supply of Link is off (LPS is Low and the internal PHY register Link_active bit is 0), the pin LKON
outputs a clock of 6.144 MHz according to the following conditions:
Link-on packet is received.
When any bit of the
μ
PD72852 PHY register’s loop, Pwr_fail, Timeout or Port_event becomes 1, and either LPS
or the Link_active bit is 0.
Table 4-2. Link-on Timing
Parameter
MIN.
MAX.
Unit
Frequency
4
8
MHz
Duty Cycle
40
60
%
Propagation delay before the Link becomes active (LPS is
asserted and the Link_active bit in the PHY register is 1).
500
ns
If LPS or the Link_active bit is 0, the Link is considered inactive.
When the Link is inactive and any of Loop, Pwr_fail, Timeout, Port_event becomes 1, then Link-on is asserted
High.
When the Link is active (both LPS and Link_active become 1) and Loop, Pwr_fail, Timeout and Port_event
become 1, Status transfer is sent on the PHY/Link interface.
The
μ
PD72852 activates the PHY/Link interface when LPS is 1, regardless of the value of the Link active bit.
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