參數(shù)資料
型號(hào)： UPD72870F1
廠商： NEC Corp.
英文描述： IEEE1394 1-CHIP OHCI HOST CONTROLLER
中文描述： IEEE1394連接1 - OHCI主機(jī)控制器芯片
文件頁(yè)數(shù)： 29/48頁(yè)
文件大小： 311K
代理商： UPD72870F1
Preliminary Data Sheet S13925EJ2V0DS00
29
μ
PD72870,72871
3.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register
The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the
Next_Item_Ptr describes the location of the next item in the
μ
PD72870, 72871’s Capability List.
Bits
R/W
Description
7-0
R
Cap_ID
Constant value of 01H. The default value identified the Link List item as being the PCI
Power Management registers, while the ID value is assigned by the PCI SIG.
15-8
R
Next_Item_Ptr
Constant value of 00H. It indicated that there are no more items in the Link
List.
3.1.22 Offset_62 Power Management Capabilities Register
This is a 16-bit read-only register that provides information on the power management capabilities of the
μ
PD72870, 72871.
Bits
R/W
Description
2-0
R
version
Constant value of 001. The power management registers are implemented as defined
in revision 1.0 of PCI Bus Power Management Interface Specification.
3
R
PME clock
Constant value of 0.
4
R
Auxiliary power source
Constant value of 0. The alternative power source is not supported.
5
R
DIS
Constant value of 0.
8,6
R
Reserved
Constant value of 000.
9
R
D1_support
Constant value of 0. The
μ
PD72870, 72871 does not support the D1 Power
Management state.
10
R
D2_support
Constant value of 1. The
μ
PD72870, 72871 supports the D2 Power Management
state.
15-11
R
PME_support
Constant value of 01100.
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