參數(shù)資料
型號(hào)： UPD72870F1
廠商： NEC Corp.
英文描述： IEEE1394 1-CHIP OHCI HOST CONTROLLER
中文描述： IEEE1394連接1 - OHCI主機(jī)控制器芯片
文件頁(yè)數(shù)： 30/48頁(yè)
文件大?。?/td> 311K
代理商： UPD72870F1
Preliminary Data Sheet S13925EJ2V0DS00
30
μ
PD72870,72871
3.1.23 Offset_64 Power Management Control/Status Register
This is a 16-bit read-only register that provides control status information of the
μ
PD72870, 72871.
Bits
R/W
Description
1,0
R/W
PowerState
Default value is undefined. This field is used both to determine the current power
state of the
μ
PD72870, 72871 and to set the
μ
PD72870, 72871 into a new power state. As D1
is not supported in the current implementation of the
μ
PD72870, 72871, writing of ‘01’ will be
ignored.
00: D0 (DMA contexts: ON, Link Layer: ON)
01: Reserved (D1 state not supported)
10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active)
11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon
LinkON being active, Power can be removed)
The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal
signal in the
μ
PD72870,72871.
7-2
R
Reserved
Constant value of 000000.
8
R/W
PME_En
Default value of 0. This field is used to enable the specific power management
features of the
μ
PD72870, 72871.
12-9
R
Data_Select
Constant value of 0000.
14,13
R
Data_Scale
Constant value of 00.
15
R/W
PME_Status
Default value is undefined. A write of ‘1’ clears this bit, while a write of ‘0’ is
ignored.
#
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