參數(shù)資料
型號(hào)： UPD75066GBA
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 29/68頁(yè)
文件大?。?/td> 640K
代理商： UPD75066GBA
29
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
7. STANDBY FUNCTION
The
μ
PD75068 has two different standby modes (STOP mode and HALT mode) to reduce power dissipation
while waiting for program execution.
Table 7-1. Standby Mode Statuses
Note
A/D converter's operation in HALT mode is possible only when the main system clock operates.
Instruction for setting
System clock for setting
Clock oscillator
Basic interval
timer
Serial interface
Timer/event
counter
Watch timer
A/D converter
External
interrupt
CPU
Release signal
HALT mode
HALT instruction
Can be set either with the main system
clock or the subsystem clock.
Only the CPU clock
Φ
stops its operation
(oscillation continues).
Can operate only at main system clock
oscillation (IRQBT is set at reference
time intervals.).
Can operate only when external SCK
input is selected as the serial clock or at
main system clock oscillation.
Can operate only when TI0 pin input is
specified as the count clock or at main
system clock oscillation.
Can operate.
Can operate.
Note
An interrupt request signal from hard-
ware whose operation is enabled by the
interrupt enable flag or the RESET signal
input
STOP mode
STOP instruction
Can be set only when operating on the
main system clock.
Only the main system clock stops its
operation.
Does not operate.
Can operate only when the external SCK
input is selected for the serial clock.
Can operate only when the TI0 pin input
is selected for the count clock.
Can operate when f
XT
is selected as the
count clock.
Does not operate.
INT1, INT2, and INT4 can operate.
Only INT0 cannot operate.
Does not operate.
An interrupt request signal from hard-
ware whose operation is enabled by the
interrupt enable flag or the RESET signal
input
Opera-
tion
status
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