參數(shù)資料
型號(hào)： UPD75066GBA
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 53/68頁(yè)
文件大?。?/td> 640K
代理商： UPD75066GBA
53
μ
PD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T
a
= –40 to +85
°
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention supply voltage
V
DDDR
2.0
6.0
V
Data retention supply current
Note
1
I
DDDR
V
DDDR
= 2.0 V
0.1
10
μ
A
Release signal setting time
t
SREL
0
μ
s
Oscillation stabilization
wait time
Note
2
Release by RESET
2
17
/fx
ms
t
WAIT
Release by interrupt request
Note3
ms
Notes 1.
Current which flows in the on-chip pull-up resistor is not included.
2.
The oscillation stabilization wait time is the time during which the CPU operation is stopped to
prevent unstable operation at the oscillation start.
3.
Depends on the basic interval timer mode register (BTM) settings (See the table below).
Wait Time
BTM3
BTM2
BTM1
BTM0
(Figures in parentheses are for operation at fx = 4.19 MHz)
—
0
0
0
2
20
/fx (approx. 250 ms)
—
0
1
1
2
17
/fx (approx. 31.3 ms)
—
1
0
1
2
15
/fx (approx. 7.82 ms)
—
1
1
1
2
13
/fx (approx. 1.95 ms)
Data Retention Timing (STOP mode release by RESET)
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
STOP Mode
Data Retention Mode
STOP Instruction Execution
RESET
V
DD
Internal Reset Operation
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
STOP Mode
Data Retention Mode
STOP Instruction Execution
V
DD
HALT Mode
Operating
Mode
V
DDDR
t
SREL
t
WAIT
Standby Release Signal
(Interrupt Request)
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