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參數(shù)資料
| 型號： | UPD753036GK |
| 廠商： | NEC Corp. |
| 英文描述： | DIODE ZENER SINGLE 500mW 75Vz 1.7mA-Izt 0.05 0.1uA-Ir 56Vr DO35-GLASS 5K/REEL |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 39/88頁 |
| 文件大?。?/td> | 483K |
| 代理商： | UPD753036GK |
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39
μ
PD753036, 753036(A)
Data Sheet U11353EJ4V0DS00
8. STANDBY FUNCTION
In order to save power consumption while a program is in a standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the
μ
PD753036.
Table 8-1. Operation Status in Standby Mode
STOP Mode
HALT Mode
Set instruction
STOP instruction
HALT instruction
System clock when set
Settable only when the main system
clock is used.
Settable both by the main system
clock and subsystem clock.
Operation
status
Clock generator
The main system clock stops oscillation.
Only the CPU
Φ
halts (oscillation
continues).
Basic interval timer
Operation stops
Operation. (The IRQBT is set in the
reference interval)
Note 1
.
Serial interface
Operable only when an external SCK
input is selected as the serial clock.
Operable
Note 1
Timer/event counter
Operable only when a signal input to
the T10-T12 pins is specified as the
count clock.
Operable
Note 1
Watch timer
Operable when f
XT
is selected as the
count clock.
Operable
LCD driver controller
Operable only when f
XT
is selected as
the LCDCL.
Operable
External interrupt
The INT1, 2, and 4 are operable.
Only the INT0 is not operated.
Note 2
CPU
The operation stops.
Release signal
Interrupt request signal sent from the operable hardware enabled by the
interrupt enable flag.
Test request signal sent from the test source enabled by the test enable flag
RESET signal
Notes 1.
Cannot operate only when the main system clock stops.
Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode
register(IM0).
2.
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