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參數(shù)資料
| 型號(hào)： | UPD753036GK |
| 廠商： | NEC Corp. |
| 英文描述： | DIODE ZENER SINGLE 500mW 75Vz 1.7mA-Izt 0.05 0.1uA-Ir 56Vr DO35-GLASS 5K/REEL |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 40/88頁 |
| 文件大?。?/td> | 483K |
| 代理商： | UPD753036GK |
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40
μ
PD753036, 753036(A)
Data Sheet U11353EJ4V0DS00
9. RESET FUNCTION
There are two reset inputs: external RESET signal and reset signal sent from the basic interval timer/watchdog
timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 9-1 shows
the circuit diagram of the above two inputs.
Figure 9-1. Configuration of Reset Function
By the RESET signal generation, each device is initialized as listed in Table 9-1. Figure 9-2 shows the timing
chart of the reset operation.
Figure 9-2. Reset Operation by RESET Signal Generation
Note
The following two times can be selected by the mask option.
2
17
/f
X
(21.8 ms : at 6.0 MHz operation, 31.3 ms : at 4.19 MHz operation)
2
15
/f
X
(5.46 ms : at 6.0 MHz operation, 7.81 ms : at 4.19 MHz operation)
RESET
Internal reset signal
Reset signal sent from the
basic interval timer/watchdog timer
WDTM
Internal bus
Operating mode or
standby mode
Wait
Note
RESET
signal
generated
Operating mode
HALT mode
Internal reset operation
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