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17
μ
PD75517(A)
Table 2-1 Addressing Modes
Bit specified by bit at the address specified by MB and mem. In this case:
When MBE = 0 and mem = 00H-7FH, MB = 0
When MBE = 0 and mem = 80H-FFH, MB = 15
When MBE = 1, MB = MBS
Address specified by MB and mem. In this case:
When MBE = 0 and mem = 00H-7FH, MB = 0
When MBE = 0 and mem = 80H-FFH, MB = 15
When MBE = 1, MB = MBS
Address specified by MB and mem (mem: even address). In this case:
When MBE = 0 and mem = 00H-7FH, MB = 0
When MBE = 0 and mem = 80H-FFH, MB = 15
When MBE = 1, MB = MBS
Address specified by MB and HL.
In this case, MB = MBEMBS
Address specified by DE in memory bank 0
Address specified by DL in memory bank 0
Address specified by MB and HL (with the L register holding an even number).
In this case, MB = MBEMBS
Bit specified by bit at the address specified by fmem. In this case:
fmem = FB0H-FBFH (interrupt-related hardware)
fmem = FF0H-FFFH (I/O port)
Bit specified by the low-order 2 bits of the L register at the address specified
by the high-order 10 bits of pmem and the high-order 2 bits of the L register.
In this case, pmem = FC0H-FFFH
Bit specified by bit at the address specified by MB, H, and the low-order 4 bits
of mem.
In this case, MB = MBEMBS
Address specified by SP in memory bank 0, 1, 2, and 3 selected by SBS
1-bit direct addressing
4-bit direct addressing
8-bit direct addressing
4-bit register indirect
addressing
8-bit register indirect
addressing
Bit manipulation
addressing
Stack addressing
mem.bit
mem
@HL
@HL+
@HL–
@DE
@DL
@HL
fmem.bit
pmem.@L
@H+mem.bit
—
Representation
format
Specified address
Addressing mode