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38
μ
PD75517(A)
3.8 BANK SELECT REGISTER (BS)
The bank select register consists of a register bank select register (RBS) and memory bank select register
(MBS), which specify a register bank and memory bank to be used, respectively.
The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction, respectively.
The contents of BS can be saved to or restored from a stack area eight bits at a time by using the PUSH
BS/POP BS instruction.
Fig. 3-11 Bank Select Register Format
(1) Memory bank select register (MBS)
The memory bank select register is a 4-bit register used to store the high-order four bits of a 12-bit data
memory address. The contents of this register specify a memory bank to be accessed. Note, however,
that the
μ
PD75517(A) allows only memory banks 0, 1, 2, 3, and 15 to be specified.
The MBS is set with the SEL MBn instruction (n = 0, 1, 2, 3, 15)
Fig. 2-1 shows the range of addressing using MBE and MBS settings.
A RESET signal occurrence initializes the MBS to 0.
(2) Register bank select register (RBS)
The register bank select register specifies a register bank to be used as general registers; a register bank
can be selected from register banks 0 to 3.
The RBS is set with the SEL RBn instruction (n = 0 to 3).
A RESET signal occurrence initializes the RBS to 0.
Table 3-5 Register Bank to Be Selected with the RBE and RBS
Remark
×
: Don’t care
Symbol
BS
MBS3 MBS2 MBS1 MBS0
0
0
RBS1
RBS0
F83H
MBS
F82H
RBS
Address
Bank 0 is always selected.
Bank 0 is selected.
Bank 1 is selected.
Bank 2 is selected.
Bank 3 is selected.
RBS
RBE
Register bank
Always 0
0
1
3
0
0
2
0
0
1
×
0
0
1
1
0
×
0
1
0
1