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參數(shù)資料
| 型號(hào)： | UPD75518GF |
| 廠商： | NEC Corp. |
| 英文描述： | CAT5E PATCH CABLES SNAGLESS, RED 3 FT |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 55/180頁(yè) |
| 文件大?。?/td> | 1595K |
| 代理商： | UPD75518GF |
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55
μ
PD75518(A)
(4) System clock control register (SCC)
The SCC is a 4-bit register for selecting CPU clock
Φ
with the least significant bit and for controlling the
termination of main system clock generation with the most significant bit. (See
Fig. 4-13
.)
SCC.0 and SCC.3 are located at the same data memory address, but both bits cannot be changed at the
same time. Accordingly, SCC.0 and SCC.3 are set using bit manipulation instructions. SCC.0 and SCC.3
can be manipulated regardless of MBE setting.
Main system clock generation can be terminated by setting SCC.3 only when the subsystem clock is used
for operation. The STOP instruction must be used for generation termination when the main system clock
is used for operation.
The generation of a RESET signal clears the SCC to 0.
Fig. 4-13 Format of the System Clock Control Register
Cautions 1. A time period of up to 1/f
XT
is needed to change the system clock. This means that to
terminate main system clock generation, SCC.3 must be set when the machine cycles
indicated in Table 4-5 or more have elapsed after the clock is switched from the main system
clock to the subsystem clock.
2. When the main system clock is used for operation, setting SCC.3 to stop clock generation
does not enter the normal STOP mode.
3. When SCC.3 is set to 1, the X1 input pin is connected to V
SS
(GND electric potential) to
prevent leakage in the crystal oscillator. When an external clock is used as the main system
clock, never set SCC.3 to 1.
4. When the four bits of PCC are set to 0001B (
Φ
= f
X
/16), do not set SCC.0 to 1. Before switching
the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other
than 0001B is set. When the system operates on the subsystem clock, the PCC bits must
also be other than 0001B.
Address
FB7H
SCC3
—
—
SCC0
Symbol
SCC
CPU clock frequency
Main system clock
Main system clock operation
Subsystem clock
Can oscillate
Subsystem clock
0
0
1
0
0
1
1
1
Oscillation stopped
SCC0
SCC3
Not to be set
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