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參數(shù)資料
| 型號(hào)： | UPD75518GFA |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 37/180頁(yè) |
| 文件大?。?/td> | 1595K |
| 代理商： | UPD75518GFA |
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37
μ
PD75518(A)
Table 3-4 Information Indicated by the Interrupt Status Flag
The interrupt priority control circuit (see
Fig. 5-1
) checks this flag to control multiple interrupts.
The contents of the IST1 and IST0 are saved as part of the PSW to stack memory if an interrupt is accepted,
then are automatically set to a one-step higher status. The RETI instruction restores the contents present
before an interrupt occurs.
The interrupt status flag can be manipulated using a memory manipulation instruction, and the status of
processing being performed can be changed by program control.
Caution The user must always disable interrupts with the DI instruction before manipulating this flag,
and must enable interrupts with the EI instruction after manipulating this flag.
(4) Memory bank enable flag (MBE)
The memory bank enable flag is a 1-bit flag used to specify the address information generation mode for
the high-order four bits of a 12-bit data memory address.
When the MBE is set to 1, the data memory address space is expanded, allowing all data memory space
to be addressed.
When the MBE is reset to 0, the data memory address space is fixed, regardless of MBS setting. (See
Fig.
2-1
.)
A RESET signal occurrence automatically initializes the MBE by setting the MBE to the content of bit 7
at program memory address 0.
In vectored interrupt processing, the MBE is automatically set to the content of bit 7 in the vector address
table for servicing the interrupt.
Usually, the MBE is set to 0 in interrupt processing, and static RAM in memory bank 0 is used.
(5) Register bank enable flag (RBE)
The register bank enable flag is a 1-bit flag used to determine whether to expand the general register bank
configuration.
When the RBE is set to 1, a set of general registers can be selected from register banks 0 to 3, depending
on the setting of the register bank select register (RBS).
When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting
of the RBS.
A RESET signal occurrence automatically initializes the RBE by setting the RBE to the content of bit 6 at
program memory address 0.
When a vectored interrupt occurs, the RBE is automatically set to the content of bit 6 in the vector address
table for servicing the interrupt. Usually, the RBE is set to 0 in interrupt processing. Register bank 0 is
used for 4-bit processing, and register banks 0 and 1 are used for 8-bit processing.
Normal program processing is being performed.
Any interrupts are acceptable.
A lower- or higher-priority interrupt is being serviced.
Higher-priority interrupts are acceptable.
A higher-priority interrupt is being serviced.
No interrupts are acceptable.
Not to be set
IST1
IST0
0
0
1
1
0
1
0
1
Status 0
Status 1
Status 2
—
Status of processing
being performed
Processing and interrupt control
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD7554AG-597-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-597-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-611-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
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